Setting SYSCLK to 48 MHz using HSI

How can we set SYSCLK to 48 MHz using HSI?

What are the steps involved in configuring the system clock to achieve 48 MHz using the High-Speed Internal oscillator?

Setting SYSCLK to 48 MHz using HSI

To set SYSCLK to 48 MHz using HSI, you need to follow a specific process. Here are the steps involved:

Setting the system clock (SYSCLK) to 48 MHz using the High-Speed Internal (HSI) oscillator requires careful configuration and enabling of different components in the STM32 microcontroller. The HSI oscillator provides a clock signal for the microcontroller, but additional steps are necessary to increase the system clock frequency to 48 MHz.

The process involves enabling the HSI oscillator, configuring the Phase-Locked Loop (PLL), and selecting PLL as the system clock source. Here is a detailed explanation of each step:

Step 1: Enable the HSI oscillator

Enable the HSI oscillator by setting the HSION bit in the RCC_CR register. This will turn on the HSI oscillator and provide the initial clock signal for the microcontroller.

Step 2: Wait for the HSI oscillator to stabilize

Check the HSIRDY bit in the RCC_CR register to ensure that the HSI oscillator has stabilized. This will indicate that the oscillator is ready to be used as the clock source.

Step 3: Configure the PLL to multiply the HSI frequency

Configure the PLL to multiply the HSI frequency to 48 MHz. This is achieved by setting the PLL multiplication factors appropriately in the PLLCFGR register.

Step 4: Enable the PLL

Enable the PLL by setting the PLLON bit in the RCC_CR register. This will activate the PLL and allow it to generate a clock signal at the desired frequency.

Step 5: Wait for the PLL to stabilize

Check the PLLRDY bit in the RCC_CR register to confirm that the PLL has stabilized. This ensures that the PLL is functioning correctly before proceeding further.

Step 6: Select the PLL as the system clock source

Set the SW bits in the RCC_CFGR register to select the PLL as the system clock source. This will configure the microcontroller to use the PLL-generated clock signal as the main system clock.

Step 7: Wait for the system clock to be ready

Check the SWS bits in the RCC_CFGR register to ensure that the system clock has been successfully switched to the PLL source. This confirms that the SYSCLK is now running at 48 MHz.

By following these steps carefully, you can set SYSCLK to 48 MHz using the HSI oscillator and PLL configuration in the STM32 microcontroller.